In the metallization of high aspect ratio vias and trenches on semiconductor wafers, it is required that the barrier and seed layer have good sidewall coverage. Physical Vapor Deposition (PVD) processes have long been recognized as having certain advantages, namely their simplicity, their cleanliness, and other long known factors. However, most applications of PVD processes in semiconductor manufacture have encountered performance limitations, which have motivated the use of otherwise less desirable processes to overcome these limitations. For example, CVD processes are often resorted to for achieving high conformity and ALD processes are resorted to for achieving ultra-thin films.
Ionized PVD deposition have been preferred for barrier and seed layer metallization in advanced IC wafers in many applications. For example, IPVD has been used for applying tantalum nitride (TaN) barrier layers for copper (Cu). Ionized PVD provides good sidewall and bottom coverage in via and trench structures. However, as the geometries shrink and as the via dimensions go down below 0.15 micrometers, ionized deposition requirements become more critical. Therefore, it is highly desirable to have an ionized PVD process where bottom and sidewall coverage are well balanced and overhang is minimized.
Many prior art attempts to provide TaN barrier layers that effectively prevent oxidation of copper due to movement of oxygen from low-K dielectric substrates have resulted in the loss of conformality of the deposited film or nitridation of the tantalum target or other degradations in process performance.
Accordingly, there is a need to provide for the PVD of barrier layers of materials including TaN that overcome the problems of the prior art. Further, there remains a need to better control step coverage of the metal or the overhang that typically develops during the deposition step.